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Working at Apple means doing more than you ever thought possible and having more impact than you ever imagined.
Summary Posted: Dec 9, 2021
Join our team at Apple developing complex digital IPs for Apple’s custom mixed-signal integrated circuits! We have already shipped hundreds of millions of chips into Apple’s existing product lines and are developing new chips for future product lines! As a member of our mixed-signal ASIC implementation team, you will be responsible for the physical implementation of design partitions, as well as chip top-level in the mixed-signal power management ICs. You will work with digital design, analog design and CAD teams to create designs with the best-in-class power efficiency and performance. Learn and use pioneering physical design and analysis flows to implement your designs. We supply silicon to Apple’s industry leading hardware development teams and collaborate closely with them. We have a close-knit, robust team in need of enthusiastic digital design engineers to develop new ASIC IP’s. We pride ourselves for being an especially diverse team that values innovative approaches to deliver creativity, high productivity, and industry leading results. Join us in building Apple’s next generation products. Do you want to be a part of building the “surprise and delight” in Apple’s future products?
* Typically requires physical design experience, with a passion to learn and grow as a physical design engineer.
* Fluent in P&R implementation, including floorplanning, clock & power distribution, timing closure, physical & electrical verification.
* Solid knowledge of PD construction & analysis flows and methodology including timing closure, noise analysis, EM/IR analysis, UPF based power verification, logic equivalence checks and DRC/LVS/PERC verification.
* Familiar with the ECO flow for functional design fixes and timing closure.
* Ability to execute to stringent schedule & die size requirements.
* Familiar with industry standard tools used and their capabilities & underlying algorithms.
* Strong communication skills.
• Deliver complex digital IPs, meeting schedule, area, power, and performance targets. • Work with logic design team to understand the architecture and drive physical implementation feasibility studies early in the design cycle. • Complete netlist to GDS2 implementation for partitions and chip-top meeting the power and performance goals. • Perform timing closure, logic equivalence, electrical verification and physical verification of the designs. • Resolve design and flow issues related to physical design, identify potential solutions, implement timing and functional ECOs, and drive the execution towards the most power efficient implementation.
Education & Experience